DESIGN OF MODIFIED MARCH-C ALGORITHM AND BUILT-IN SELF-TEST ARCHITECTURE FOR MEMORIES

Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM, ROM, DRAM, etc., are the different types of memory and it becomes difficult to test the memory because of the complexity of the design increases day by day. The testing of memory is very difficult as it’s required many test patterns. In this paper, a new test architecture is designed using a response analyzer and checker to detect a fault on a chip, and the modified MARCH C algorithm is also proposed to check the fault in the memory in the shortest time.


INTRODUCTION
Testing the complete memory is a difficult task. Testing can be done with help of fault models in the Built-in self-test (BIST) architecture. Many fault models are available to test the memory. Here we have used traditional faults models to test the memory. Out of various available algorithms MARACH algorithms provides better fault detection and coverage. In this paper, we proposed a new architecture that consists of the checker, response analyzer, memory unit and a BIST controller with Modified March C algorithm. By using a checker, we can get more précised output.

PROBLEM STATEMENT
Memory testing is used to identify that the memory is capable of writing and reading the correct data or not. March based algorithms can identify and locating the fault types which can help to check the design and manufacturing errors. The quality of the test is strongly dependent on the fault model in terms of its fault coverage, its test length as well as the test time required.
In this paper Modified MARCH C-the algorithm is implemented to detects the maximum fault. In addition to that Response analyzer and Checker are included in this architecture to identifies more faults with high precision.

TYPES OF FAULT IN THE MEMORY
There are 3 types functional faults models involved in the memory: 1. Memory cell faults.

ADDRESS DECODER FAULTS (AFs)
It occurs in the address, it can be: Cell not accessed by an address, many cells are accessed by an address, cell accessed by many addresses.

DYNAMIC FAULTS
1. Recovery faults: Part of the memory cannot recover fast enough from a previous state.
2. Disturb faults: victim cell forced to 1 or 0 when we read or write aggressor cell (maybe the same cell).
3. Data Retention faults: Because memory loses its content spontaneously, data cannot be retrieved.

MARCH ALGORITHMS
The The response will be 0 or 1 if the test algorithm reads a cell, and they are specified as R0 and R1, respectively. Similarly, writing a 1 into a cell is denoted as W1 and writing 0 as W0.

EXPLANATION AND RESULTS
Built-In Self-Test (BIST), test generation and response evaluation hardware are included on-chip so that in-circuit tests can be performed with minimal need for external test equipment, if any. The BIST technique is a common technique to test memories (RAM and ROMs).

This architecture consists of BIST Controller, Memory Under Test (MUT), Checker and
Response Analyzer. Clock signal becomes to enable the BIST controller to starts working.
The BIST controller gives the control signal to the memory. Then the memory undergoes read or/write operation according to the March algorithm.
Then the output from the memory is given to the checker. The checker compares the output from the memory to the data stored inside it. Whenever the fault occurs the checker gives the error signal, the original data along with the address to the response analyzer.
The response analyzer is used to switch the controller from normal to repair mode. Whenever the repair mode becomes to enable the controller automatically enables the write signal to repair the fault according to the address and data given by the response analyzer. After the repair operation gets completed the ref signal becomes enable to indicate that fault is repaired. As the continue signal becomes to enable the controller switches to normal mode.
This process is continued until the end of the operation. The export mask address signal is used to indicate whether the fault is repairable or not. In this way, this test architecture is used to test and repair the fault in memory with maximum accuracy.

CONCLUSION
MARCH tests are extensively being used today for functional testing of memory technologies.
They are more efficient with better fault coverage than the older classical pattern. In this project modified MARCH C Algorithm with modified BIST architecture are proposed.
With this simple BIST architecture and modified MARCH C, testing time can be reduced because two read/write operations carried out in a single clock time. So, Testing Speed can also be doubled. It also provides better fault coverage as MARCH C algorithm covers most of the faults in the memory.

ACKNOWLEDGMENT
We thank the ECE department of Kalasalingam Academy of Research and education, Krishnankoil for supporting this research by providing their center for VLSI lab facility.
The Facility which is sponsored by Department of Science and technology (DST) under Fund for Improvement of S&T Infrastructure (FIST) Scheme.