TEST TIME OPTIMIZATION BY REVISITING NOTES IN VLSI BIST TECHNIQUE

An effective method for test time minimization in Built In Self Test (BIST) using graph theory concept with revisiting of node is incorporated in this article. Here the shortest Hamiltonian path of ISCAS89 benchmark circuit s396 is taken as an example. Minimum spanning tree with revisiting nodes is applied for s386 circuit that optimizes the time cycle for testing. Result shows that minimum spanning tree with revisiting the nodes will reduce the time cycle without compromising the test quality. Hence an effective testing is achieved using graphical approach.


INTRODUCTION
In this super fast technical generation the growth of technology is massive in both technical and product aspect. Testing is an essential part which deals with the quality of the product before a microelectronic product is launched in the market where BIST is a testing scheme that is capable of finding faults in integrated circuits (ICs) to make faster testing at lessexpensive with low power constraints (Girard, Nicolici, & Wen, 2010). It plays a vital role in electronic industry because a device that needs to be tested at higher level (levels being: Chip -board -system -system in field) costs 10 time (and possibly more) that of cost of testing it a lower level. Digital testing is declared as testing a digital circuit to validate that it performs the particular logic functions and in appropriate time. In case of VLSI testing, it is not of much concern as how many chips are binned as flawed; rather important is how many flawed chips are binned as normal. So, trade and industry expects "VLSI testing" is to result in an accuracy of perfect chips with its functionality. Optimized test time and scheming test power are contradictory targets and therefore optimization of testing for both attributes is challenging. This topic has been addressed in the recent literature (Nicolici & Al-Hashimi, 2003;Sakurai & Newton, 1990;Shanmugasundaram & Agrawal, 2011;Shanmugasundaram & Agrawal, 2012;Gogoi & Kalita, 2014;Venkataramani, Sindia, & Agrawal, 2014). The BIST vectors are speedy than ATE in terms of application time, thus follow-on improvement in test time with low power (Larsson, 2006). The test vector application time ratio between ATE and BIST is represented by "α". If α= 100 than the application time of a vector in ATE is 100 times longer than the vector application of BIST (where α >1).The total time required for test is equivalent to the addition of required number of time cycles to travel from source node to destination.

PRIOR WORK
A modern approach is introduced to minimize the test time for power constrained tests (Biswas, Das, & Petriu, 2006;Das et al., 2008;Shanmugasundaram & Agrawal, 2011 implements a monitor to observe the movement in the scan chain of a built-in self-test (BIST). According to the switching activity the test clock frequency varies from high to low both the parameters are inversely proportional i.e., test clock frequency raise if there is low switching activity in the scan chain else falls. This approach attains 20-50% reduction in test 3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254 -4143 Edición Especial Special Issue Marzo 2020 time of BIST circuits with a little area overhead. Reusable scan chains (Lai, Kung, & Lin, 1993) and pattern overlapping (Zhou, Ye, Li, Wu, & Ke, 2009;Bryant, 1986;Tehranipoor, Nourani, & Chakrabarty, 2005;Alpert et al., 2018) eradicates unwanted scan chain operations using patterns that bear a resemblance to the previous pattern, so the number of scan shifting is minimized.
Hence high reduction is achieved on availability of such patterns. The single fixed order twisted ring-counter design proposed in (Tharakan & Mathew, 2015)

TEST PATTERN SELECTION
All VLSI chips after the manufacturing process are applied for fault analysis, in such a case it is not possible of generating all the test vectors, at the same time different patterns detects the same fault which increases the complexity of test vector and its storage requirement.

PROPOSED METHOD
In this paper minimum spanning tree is introduced rather than Hamiltonian path (Hamiltonian path is a path which visits each vertex exactly once and also returns to the starting vertex) in the graphical construction of the c17 & s386 benchmark circuit.
Minimum spanning tree is a tree in a graph that spans all the vertices and total weight of a tree is minimal. Addend patterns are in the form of 2 n +1 & 2 n + 3 are taken to compare the Hamiltonian path time and minimum spanning tree time cycles.

Figure 2.
Minimum spanning tree of c17 with Addend patterns are in the form of (2 n + 1).
The shortest Hamiltonian path for c17 circuit is 28 14  31  17 11 (1, 1, 2, 5) with corresponding weights and its total weight is 9 but in case of minimum spanning tree 4 time cycle are required (Figure 1 & 2). For Addend patterns are in the form of 2 n + 3 and the Hamiltonian path through 1728 113114 and their corresponding weights are (1, 2, 4, 3) totally 10 time cycles are involved whereas in minimum spanning tree with revisiting it is reduced to 7 which denotes that 14 times cycles (Figure 3 & 4) are required for testing.    Revisiting can reduce the testing time, here s396 benchmark circuit is taken as example which deals with 7 inputs and therefore 2 k test vectors are required to test the circuit i.e., 128 test vectors. A min and A vec are tabulated to derive the s396 circuit's graphical representation.
All odd value sequence from 0 to 127 is taken in account for A min and Avec calculation.
The shortest Hamiltonian path for s396 circuit is 6  21  88  5 1114 (1, 5, 3, 2, 1) with corresponding weights and its total weight is 12 but in case of minimum spanning tree 11 time cycle are required ( Figure 2). Figure Figure 6. Hamiltonian path of s386 with Addend patterns are in the form of (2 n + 1).

Figure 7.
Minimized time spanning tree of s396 with Addend patterns are in the form of (2 n + 1).
For Addend patterns are in the form of 2 n + 3 the Hamiltonian path through 1421 885611 and their corresponding weights are (1, 1, 9, 11, 1) totally 23 time cycles are involved whereas in minimum spanning tree with revisiting it is reduced to 14 which denotes that 14 times cycles ( Figure 3) are required for testing.

CONCLUSION
In this paper we have presented a graph theory concept called minimum spanning tree with revisiting nodes instead of Hamiltonian path for c17 & s396 benchmark circuit which results in optimized test time. Result shows that minimum spanning tree with revisiting the nodes will reduce the time cycle for testing. The above mentioned Table 7 & Figure 10 shows that minimum spanning tree effectively reduces the number of test time cycles for testing. In future it can be implemented to test nano memories.