Design and optimization of reversible look ahead carry adder and carry save adder

A circuit is said to be reversible if inputs and the outputs are equal. Reversibility focused mainly to bring down power to zero. In modern centuries, gates with reversible logic has arose together as notable vital approaches for power optimisation based on application. Reversible logic is leading area in power consumption. Based on its application, its emerging trend in power consumption. In ideal situations, reversible circuit yield nil power. In this paper, new design of the look ahead carry adder and carry save adder designed and it is optimized with the previous existing binary logic gates. Minimizing the garbage output and replacing the binary logic gates by reversible logic gates. To develop low power circuits, reversible circuit is necessary.


INTRODUCTION
Look ahead carry adder is a type of digital adder. In this circuit, speed can be increased by reducing the required time. Generated carry bit calculated before summing so that it can reduce the time delay. The design of ripple carry circuit is modest, but it has timeconsuming delay in the circuit due to several gates in path carry flows from LSB to MSB. Therefore, in this paper designed an alternate design, look ahead carry adder. For designing look ahead carry adder, transform ripple carry design to strategy, which reduce the number of bits to two level bit logic.
By using carry-save adder design sum up multiple binary numbers. When compared to other adder design, carry look ahead adder design be at variance in dualistic outputs that has same aspect as inputs, first output has been series of half done sum and next output has been series of carry.

A. NEED FOR REVERSIBLE LOGIC
Reversible circuits are effectual than irreversible because of information loss which leads to energy loss. Due to information loss in irreversibility, it dissipates more power. To reduce power, circuit designed with reversible logic. At last, reversible circuits can be viewed as distinct instance of quantum circuits since quantum progression must be reversible.

B. CONDITIONS FOR REVERSIBLE COMPUTATION
Reversible computation satisfies the conditions.

The foremost State:
Formost state is logical reversibility in which any settled device to be reversible state and the input and output should be unambiguously recoverable from one another.

The second State:
The second state is physical reversibility, the device in reality run backwards, i.e., each operation converts no energy to heat and produces no entropy. 3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254 -4143 Edición Especial Special Issue Marzo 2020

Representation of a reversible circuit truth table
In view of the fact that we are dealing only with bijective functions, i.e., permutations, we signify them using the pedal system which represented by dislodge cycle of functions.
S n , denoted as set of all permutations of n indices and S 2 n mentioned as set of objective perform with n input binary bits. Let us Toffoli's Gate and its corresponding truth table.

SWAP Gate:
Reversible gate, called the SWAP (S) gate which interchanges the input.

Toffoli's Gate:
In Toffoli Gate (Agarwal, Choudhary, Jangid, & Kasera, 2017), all the inputs that is from1 to (n-1) are mapped to its corresponding outputs. The final output is coordinated by inputs from 1 to (n-1). To upended and pass the nth input make all inputs as 1 else pass original output. The first two inputs corresponds to outputs and the third output controlled by first two input and invert it. The truth table has been shown in Table. MTSG gate: In MTSG gate (Agarwal et al., 2017) four number of inputs and outputs are used. By this design the one bit full adder is designed.

PROPOSED ADDER ARCHITECTURES
This deals with the Design and operation of the proposed look ahead carry adder architecture using Peres gate based on the existing adder architecture. The proposed architectures are implemented by replacing the three block's (Peres full adder) Peres gates and peresfull adders with reversible logic gates to obtain the better performance compared to conventional logic.

Design I
In this sector look ahead carry adder using Peres logic is proposed. As we know the Peres logic already, it is pretty much easier to propose this type of adder using the Peres reversible gate. The Peres full adder is already proposed (Somani, Chaudhary, & Yadav, 2016;Lisa, & Babu, 2015).
Whenever the quantum cost of the Peres gate is said to be four and the Peres full adder consist of two Peres gate, which proposes the quantum cost of eight. In addition, the minimal number of reversible logic gates used for proposing a 4 bit look ahead carry adder is 32. This design proposes the 4 bit look ahead carry adder design consist of four sum elements and a carry output. This second design is proposed by using three types of reversible gates (Peres, Toffoli, Feynmann) (Somani et al., 2016) although it is already proposed through the survey that the gates quantum cost (Peres, Toffoli, Feynmann) (Somani et al., 2016) are 4,5 and 1 respectively. By proposing this adder the quantum cost and the count of garbage outputs are also reduced. The above design proposes a design with four sum elements and a single carry output. And this design has a quantum cost of 18 for a single bit adder.

B. PROPOSED CARRY SAVE ADDER
This deals with the designing and optimization of the carry save adder by replacing the conventional logic gates by the reversible gates. By considering the minimal quantum cost containing design as the best design. Proposed 4 bit carry save adder is designed Peres full adder. Source: (Somani et al., 2016). This design proposed by using the MTSG gates.

SIMULATION RESULTS
Proposed reversible adder circuit is more proficient than existing method. Based on the comparative analysis, proposed design can be easily realized. In existing design, logic gate 3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254-4143 Edición Especial Special Issue Marzo 2020 used instead of that in proposed work reversible gate such as Peres used to understand the circuit. The circuit realized using reversible Peres gate to reduce the logical calculation. Also in terms of hardware complexity proposed work is efficient than exiting circuit.
All the simulations have been done using XILINX 9.2i and Model sim Altera 6.3g_p1.

SIMULATION RESULTS OF PROPOSED ARCHITECTURE
Design I

HARDWARE AND SOFTWARE USED
All simulations have been done using Xilinx ISE 9.2i.

APPLICATIONS
Applications based on reversible logic concept are listed.

CONCLUSION
Look ahead carry adder is designed with reversible logic gates. Proposed design optimized with existing design in terms of reversible gate operations.  Reversible circuit design strategy is used to reduce the complexity and circuit cost.
Distinguish the circuit with reversible systems, which performs more number of complex operations. Based on the reversible circuit design main factors like garbage outputs, quantum cost and delay of the circuit reduced. In addition, circuit complexity reduced by reducing the reversible gates. This work customs basic step in constructing complicated reversible systems,which can perform more comple x operations. Based on logical synthesis alternative design can be implemented. To decrease system design and manufacturing cost VLSI system implemented with one type of modular building. To reduce quantum cost and gates count, further design can be implemented using other reversible logic gates.