PERFORMANCE ANALYSIS OF THE QUANTUM PROCESSOR: BASED ON REVERSIBLE SHIFT REGISTER USING QCA

The concept of the reversible logic depends on the dominant modules of a processor that has motivated to obtain the performance analysis of the quantum based processors. In continuation to this discussion, the shift register can be studied with the use of the reversible logic which is capable of shifting the bits of the information towards both side i.e. left and right. In this process of the analysis of the quantum processor, the Quantum Computational Automata (QCA) as well as Verilog, software has been used so as to simulate the parameters of the device and then obtain the characteristics of the device. In this discussion, a reversible logical computing based approach has been mentioned that can be used in the ALU of a quantum processor with the help of D-type FFs or its combination that act as an inevitable and the most crucial basic building block in the design of quantum processor. This circuit has been designed and analyzed for the most dominant parameters, say, size of cell, number of cells used, delay, temperature dependency, power dissipation, etc. This proposed circuit which acts as an alternative to the CMOS technology, has been analyzed for a typical range of the power dissipation (650 – 750 meV), temperature range (1ºK – 10ºK).


INTRODUCTION
The QCA is the foremost and potentially promising technology which has been accepted for the typical Nano range of the frequency in the device implementations. In other words, we can say that this QCA has been emerged as the solution to the limitations of the CMOS Technology existing in the range of microns or micro of the frequency i.e. in terms of speed or delay of the data transmission, density or area in terms of the number of quantum cell used, etc. Due to this unique feature of the quantum computing with the help of QCA has emerged as a fantastic approach in the design and implementation of the device that provides the desired characteristics and performance. The demonstration of the QCA technology has been done simply by implementing it with Quantum Dots i.e. metal dots at quite predominant range of the parameters, say, temperature, pressure, etc. .
It means that these metal dots have been used in the design of various basic blocks or modules of this system such as QCA based wires, logic gates, memories, and reversible gates. As per Moore's law, it has been seen that after every ten years the density of the components fabricated on the chip gets almost doubled that becomes the most significant limitations of the CMOS Technology. In other words, it has been observed that size and area of the fabricated board keeps on increasing that in turn increases the overall size of the processor. Due to this reason, the power dissipation i.e. loss of energy is quite large in this technology, delay is also quite huge. All these limitations are taken care by simply making use of QCA tools that operate in the range of nanoscale. In this technology, the fabrication techniques of the chips played quite dominant role with the desired performance such as preparation of dyes for the ICs which includes quite complex structure and resistant to various degradation methods. The fabrication process of the ICs includes the standard techniques as compared to the conventional methods of separating the impurities such as oxidation, membrane separation, precipitation, etc. .
An important problem of the design and implementation of reversible logic based universal shift register for a quantum processor, especially, the ALU of desired bit. In the context of designing the highly efficient ALU, one must formulate the study and implementation of the important modules of the ALU such as comparator, shift register, logic gates, memories, etc. 3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254-4143 Edición Especial Special Issue Abril 2020 with the help of the reversible computing. In this discussion, the problem has been based on designing and implementing a reversible logic based shift register that is bidirectional in nature. Now in order to obtain the understanding of this technique, one must obtain the comparative analysis of this concept with the prevailing technology i.e. CMOS Technology.
For the proper understanding of this technology, one must discuss the development process of this technique with the help of ITRS in the scale of 45nm (Tiwari et al., 2017).

QUANTUM CELLULAR AUTOMATA (QCA)
With the development of this technology in the nano scale range, various devices have been designed and implemented which in turn becomes the basic building blocks of most of the system, say, ALU which is designed for quantum processors.     (1) Logical gates as shown in below Figure 5. QCA Based Memories as shown in the below given Figure 6. These gates operating on reversible computing have equal number of inputs and outputs as compared to the traditional gates and have bi-mappings between input vectors and output vectors; consequently the input data can be recreated from the output vector states. A reversible gate with n inputs and n output is known as n * n gate as shown in below Figure   7. Feynman Gate is a 2 * 2 reversible gate as shown in the below Figure 7 which is also known as CNOT, i.e., controlled NOT Gate. The input (A, B) and output (P, Q) relation is as follows i.e. (Roohi & Khaemol, 2014). (2) On the contrary, Fredkin gate is a (3 * 3) conservative reversible gate as shown in the below Figure 8. The relation between input vectors and its output vectors is as follows (Walus et al., 2004). (4)

REVERSIBLE COMPUTING BASED SHIFT REGISTER MEMORY
(8)

Reversible Universal Shift Register for Quantum Processor (ALU):
In this discussion, the author has extended the above discussion of designing and Similarly, the below given Figure 11 provides us an alternative approach of the design of    The above Figure 12 shows another configuration of designing the proposed model with SIPO data flow tendency with the use of Delay Flip Flops.

Reversible Logic Gates Based D Flip Flop:
Another technique of designing the circuit of Delay Flip Flop has been considered for the quantum processors, especially, the modules which are dominant for the design of ALU.
The below given Figure 13 shows the Delay Flip Flop using the QCA Designer Tool 2.0.

SIMULATION RESULTS & DISCUSSIONS
The performance of the proposed model discussed based on the most pre-dominant parameters of the reversible logic based shift register i.e. area of the cell, number of cells used, delay i.e. speed of the data transmission between output and input of the circuit.
Thus, based on the behavior of these parameters, using QCA Designer Tool 2.0, writing the codes for the structure behavior of the proposed model using VHDL and Verilog codes.
In this proposed circuit, the author has made the use of the reversible gates with best efficiency i.e. Fredkin & Feynman gates. From this simulation as shown in Figure 15, it has been observed that the power dissipation or the loss of information of these two reversible gates is quite less as compared to others. Due to this reason, these gates are quite common in use for the development of various modules of the quantum processors. These reversible gates have got a limitation due to tunneling effect of the energy which in turn causes the increase in the power dissipation. This discussion of the author has been supported with the help of below give Table 1 and Figure 16 that gives the information of the power dissipation of the proposed model with respect to the circuits of the reference work done by others.  This discussion based on the performance of the proposed circuit of universal shift register has been carried out based on the delay comparison, cell count comparison, area comparison has been simulated with the use of some suitable software as shown in below Figure 17. The below given Figure 17 fives the behavior of the universal circuit with the reference work carried out by other researchers in terms of the temperature with a mean polarization of the quantum cells i.e. XE-001 neV. From the above discussions, it has been found that the power dissipation and the loss of energy of the proposed circuit using majority gates using the reversible computing ability.
On this basis of these all, the author has concluded with the simulated result supported by Table 1 providing the comparative analysis based on the considered parameters. The above Figure 18 shows the overall performance of the proposed model of the universal shift register for the quantum processor, i.e. the ALU which is using the reversible logic based computing as compared to the 45 nm CMOS Technology.

CONCLUSION
In this paper, the authors has undergone with a non-exhaustive literature survey to obtain the problem enunciation of this problem. In this process, the author has taken the most dominant parameters i.e. number of cells, delay and area of the quantum cells of the reversible gates to design and implement an innovative circuit of universal shift register that can be used for the design of ALU of the quantum processor. In this context, the author has made the use of the circuit of 4:1 multiplexer in addition to the reversible gate based D flip flop in order to design and implement the 4-bit as well as 8-bit shift register with SIPO and PIPO based data transmission. This proposed circuit which acts as an alternative to the CMOS technology, has been analyzed for a typical range of the power dissipation (650-750 meV), temperature range (1ºK-10ºK).