DESIGN OF RECONFIGURABLE MEMS-PLL FOR HIGH END TUNING CIRCUITS

The designs of memristive circuits become more demanding since the evaluation of miniaturized models are rapidly increasing every year. Here a novel Memristive Digital Phase locked loop circuit is evaluated. In the existing research works it is found that design of analog domain memristor creates enormous noise and limitations. In the Proposed system, Design of MEMS activated DPLL is evaluated. Digital PLL plays a major role in high-speed communication platforms. The benefits of PLL like jitter free clock generation, stabilized regulation and less resilient is improved even more in MEMS controlled DPLL we call as MEMPLL. In the proposed system an adaptive DPLL vary with respect to Memristor is developed here. The evaluation of memristor emerging in the field of large memory architecture and complex tuning. The advantage of storing the N info at the memristor can vary the development circuits in a reconfigurable manner. Here, the parameters are compared by DCO and ADC method and the power is achieved by 3.0 mw.


INTRODUCTION
Memristor is nothing but a resistor with memory in which the resistance values can be varied which depends upon the amount of electrical charge applied to the programmable emulator (Borghetti et al., 2010). A memristor is a passive two terminal component in which the internal resistance is tunable with respect to the low-level digital clock which we call as memristor control clocks. N combinations of Memristor constants are generated (Chua, 1971). Since all passive devices work with the base of ohms law the parameter variation in memristor can tune the Voltage and current oscillations too (Williams, 2008).
A traditional Phase locked loop system takes a processing time and locking time when the input transition and output stability reachable depends on the tuning factors of the PLL circuitry. Phased detector here we call as delay detector is used to detect the difference in the time period and when comparing with the feedback signal received after the N-Counter (Borghetti et al., 2010).
SYSTEM DESIGN: MODELSIM 6.3 a mentor graphics tool is used to simulate the RTL code whereas XILINX 12.5 is used for FPGA implementation. Architects of digital systems are unavoidably looked with the undertaking of testing their structures. Each design can be made out of numerous parts, every one of which must be tried in disengagement and afterward incorporated into a structure when it works effectively. To confirm that a plan works accurately we utilize simulation, which is a procedure of testing the structure by applying inputs to a circuit and watching its conduct. The output of a simulation is an arrangement of waveforms that indicate how a circuit acts dependent on a given inputs of information sources.

MATERIALS AND METHODS
Semiconductor based memristance can be designed by the semiconductor industry, like how they designing the diodes, transistors, inductors, capacitors etc. In our project we are experimentally showing the working of the MEMRISTOR (Strukov et al., 2008) and their few useful applications (Chen et al., 2015). We designed a concept called Memory which is capable of storing the calculated resistance values. Calculating resistance values and storing in the Memory.
Initial resistance value to be 100 ohms.
Maximum resistance value to be 10 kilo ohms.
In between a sweep of resistance with an increment step size of 38.66 is added up. That is, default 100 ohms.
If one step increase in input voltage, now resistance value will be 100+38.66 = 138.66 ohms, If input voltage increased 2 steps, now resistance value will be 100+(38.66 x 2) = 177.32 ohms, like this the resistor values are being calculated and stored in a memory designed using a "n" Bit Multiplexer.

MEMRISTIVE DPLL
PLL is used to generate a stable oscillating frequency of clock with having the input of any unknown clock with less stability or we call as jittered clock. The ability of PLL to enhance the performance of oscillating when reaching the locking stage helpful to many communications systems and medical equipments depend on the usage of phase locked loop (Li, Mazumder, & Chua, 2004

WORKING PRINCIPLE
In any VLSI systems the source clock is normally the global clock generated from the crystal oscillator. The global clock generally called as GCLK is further used to clock tree synthesis (Pickett et al., 2009). Global reset is connected to hardware reset which is active high reset.

REFERENCE CLOCK GENERATOR
A simple clock tree synthesizer is here called as a reference clock generator since reference generators are used to divide the clock, multiply the clock frequency, generate the unique pulses, timing control pulses, etc. (Amarú, Gaillardon, & Micheli, 2014 sequential mux sometimes; the mux control is synchronized with clock too (Wang et al., 2017).

MEMRISTIVE COMPARATOR
Memristor based comparator is used here to compare the input unknown clock with the reference clock. Depends upon the tuned memristor value the performance of the comparator got changed .

FEEDBACK FACTOR
When the tunable memristor controls the flow of comparator operation the tunable factor gets changes through the memristor. The output depends upon the tunable factor present in the comparator feedback resistor Rf.

LOOP FILTER
Loop filters are used to remove the noise present in the path of the clock generator. Peak noise is removed through it. A digital filter is used here.

MEMS-DCO
This is an interesting module of MPLL that the tunable comparator result and further fetched to digitally controlled oscillator. The digitally controlled oscillator is synchronized with the memristor value so that the tunable factor is directly proportional to the oscillation capacity of the DCO.

PLL OUTPUT
Ultimately the tunable Memristor controls the majority of DCO operation and Comparator operation which act as key factor for digital PLL locking state. Hence the output produced here will be clearly a stable clock with equal duty cycle and jitter free which can be generated at the output pin of the DPLL after the locking condition occurs .

DESIGN OF MEMRISTOR
The below shown result clearly depicts how the memristor tuned by simply applying the digital input in the form of digital bits here we declared as in volt. 4 bit configuration is designed here as a prototypic model (Abdalla & Pickett 2011). The same platform can be used for N number of configurations. 2 power N tunable memristor can be generated. The memristors are usually depicted as artificial intelligence too since we can derive any kind of analog circuit with the help of memristor FPGA combination (Shilpa & Jawahar, 2019;Shilpa, Jawahar, & Karthik, 2018).

SIMULATION RESULT OF PLL USING MEMS
Digital PLL has enormous advantages in communication systems and high-end processing designs. The implemented Tunable DPLL varies in time at every oscillating input which can be purely jitter free and glitch free. Low power techniques such as Clock gating and power gates are used in the behavioural model to design the RTL architecture hassle free (Lee & Mazumder, 2008).

SCOPE MONITORING OF MEMPLL
The operating frequency of scope will be minimum 100 MHZ henceforth the tunable mem PLL is clearly monitored here.  The future extension of the proposed work would be improved by replacing the DPLL with DDS Digital Data synthesizer, henceforth the synthesizer is further we call as MEMRISTIVE DDS.