OPTIMIZATION OF MULTIPLIER IN REVERSIBLE LOGIC

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INTRODUCTION
One of the foremost issues in VLSI design is reducing power. In early days, due to information loss irreversible logic leads to power dissipation (Zhirnov et al., 2003). When one bit information lost, it leads to dissipate at least KTln2 joules of energy, where K=1.380650 x 10-23 m2kg-2K-1 (joules Kelvin-1) is the Boltzmann's constant and T is the temperature (Zhirnov et al., 2003). Reversible logic blocks do not lose information because it has internally zero power dissipation. To eliminate KTln2 joules of energy dissipation, circuit must be developed with reversible logic gates.
In the subsequent, based on the reversible logic multipliers are synthesized. Initially multipliers synthesized based on Toffoli circuit (Karatsuba & Ofman, 1963;Islam et al., 2009). Also, multiplier can be synthesized based on different reversible gates. In addition to that, multipliers have been proposed with large bit-width.
This paper proposes a multiplier in reversible logic with large bit-width. Two methods are projected, the foremost method is hierarchical method and another one is Karatsuba method applied to the application of FFT.
Respite of the paper systematized as follows. Reversible logic gates ideas and necessity described in Segment II. In Segment III, basics of reversible functions and circuits are discussed. Segment IV provides algorithm of proposed work. Segment V provides the design of Hierarchical and Karatsuba method. Segment VI determines the conclusion.

REVERSIBLE LOGIC GATES
In segment II, basic reversible logic gates are described which is being used in the design.

BASICS OF REVERSIBLE LOGIC
Demarcation 1: A reversible function is defined as if (1) its amount of outputs is same as the amount of inputs and (2) it plots every input design to a distinctive output.
Reversible function is required to be embed in irreversible to reduce data loss, which requires circuit lines to produce constant inputs and garbage outputs. The least count of circuit lines is added, and it determined by number of existences of the most numerous output pattern (Toffoli, 1980). Reversible functions realized based on restrictions as if fan-out and feedback are not indorsed (Wille & Drechsler, 2009 lines set denoted as X and with t 62 C the target line denoted as t = xl. The target line is inverted when control lines set assigned as one, that is., When control line is empty the input vector of the gate has been charted to    along with the product c = 5c4c3c 2c1c0. To realize this kind of multiplication we required 3 controlled increasers. a0 is control the initial controlled increaser. In addition to that it temporarily added 2 nd factor b to last 3 LSB of product c2c1c0. Carry writes over to third MSB bit c3. a1 is control the 2 nd controlled increaser. In addition to that it temporarily added 2 nd factor b with product c, i.e. to c3c2c1. Carry writes over to second MSB bit c4.
a2 controls the 3rd controlled increaser. In addition to that it temporarily added 2 nd factor b with product c, i.e. to c4c3c2. Carry writes over to MSB bit c5.

KARATSUBA METHOD
In this segment Karatsuba's algorithm, based multiplier designed with divide and conquer method. Based on this method multiplication realized by multiplying two factors with smaller bit-width and additionally perform some less expensive operations. Consider an n-bit multiplication with m = 2.k, Both multiple factors (example.   init a n , b n , c 2·n+1 with 0 6 7 k := 8 init d, e (k + 1 bits), f (2 · k + 2 bits ) with 0 Multiplication performed by the hierarchical approach when turning point is greater than the bit.

KARATSUBA METHOD
For example, the same values can be multiplied using karatsuba method representing with 16bits.

CONCLUSIONS
This paper proposes a multiplier with very large bit-width using reversible logic. The Hierarchical method only applicable for small bit-width but the Karatsuba method applicable for large bit-width. The results are compared using synthesized result of device utilization of the two methods. The Karatsuba method is better than the Hierarchical method because the device utilization was more in the case of Hierarchical method that is mention in Table 1. The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware.
In nanotechnology applications this multiplier can be used to construct complex system. This result is taken by 16bit multiplication of two binary values 0000000000001011 and 0000000010000001. Source: own elaboration.